Integrated circuits are often formed using an application specific integrated circuit architecture, which tends to reduce the design costs of the integrated circuit by mixing and matching pre-designed functional blocks in a somewhat customized arrangement to produce an integrated circuit according to a customer's specifications. One functional block of such a customizable integrated circuit design is referred to as Reconfigurable RAM, or RRAM for short.
RRAM contains sets of memories of the same type that are placed compactly within a memory matrix. An RRAM, as the term is used herein, is a mega cell that can be considered as a set of memories with built-in self testing and built-in self correction.
During the design phase of integrated circuits, a delay analysis is typically performed, where the delays of the nets within the integrated circuit are characterized. For some integrated circuit designs this is not such a difficult problem. However, for very complex circuits, such as RRAMs, there may be on the order of about twenty thousand different nets to investigate. The repeated and separate consideration of each one of these nets for each change that is made to the design can place a serious burden on the delay analysis tool.
What is needed, therefore, is a system that enables more accurate and timely mathematical modeling for the design of RRAM.